The present invention relates to voltage-controlled oscillators, especially voltage-controlled oscillators used in a phase locked loop ("PLL") circuitry.
An example of phase locked loop circuitry is shown in FIG. 1. The phase locked loop 10 includes a voltage-controlled oscillator 12. The output of the voltage-controlled oscillator is sent to a divider 14. The divider produces one output pulse for every N input pulses. The output of the divider is compared with an input synchronizing pulse in a phase detector 16. The phase detector 16 produces a correction signal on line 18 which is sent to the low-pass filter ("LPF") 20. The filtered correction signal, such as a control voltage, is used to control the frequency of the output of the voltage-controlled oscillator ("VCO") 12. The output on line 22 of the voltage-controlled oscillator 12 will have a frequency "N" times the frequency of the sync pulses.
FIG. 2 shows another prior art phase locked loop circuit 24. The phase locked loop circuit 24 is used in systems when the frequency of the voltage-controlled oscillator is not a harmonic of the synchronizing signal (e.g. a horizontal synchronizing signal of television signal) and another frequency (e.g. a synchronizing pulses) is used for reference. For example, the output clock signal can be a dot clock for the generation of the on-screen display ("OSD") in a television application when there is no incoming video signal. In that case, a reference frequency from a crystal oscillator can be used as the system clock. Referring to FIG. 2, the output of the first voltage-controlled oscillator 26 is sent to the divide-by-N counter 28. The output of the divide-by-N counter 28 is compared in the phase detector 30 with the reference frequency provided from a crystal oscillator. The correction signal is filtered in a low-pass filter 32 and sent to both the first voltage-controlled oscillator 26 and the second voltage-controlled oscillator 34. In the phase locked loop as shown, the second voltage-controlled oscillator 34 is synchronized using the sequence of synchronizing pulses. Independently of the synchronizing pulses' stability, the second voltage-controlled oscillator output at line 36 will be in phase with the synchronizing pulses.
This approach relies on the first and second voltage-controlled oscillators having identical characteristics. Specifically, the output of the first voltage-controlled oscillator is sent to the feedback loop, but the output of the second voltage-controlled oscillator is not. In fact, both the voltage-controlled oscillators will inevitably have different parameters, especially the sensitivities to the control signal and to the noise. If this phase locked loop circuit is used in a television application, the difference in VCO parameters can cause, for example, differences in the OSD size due to differences in frequency of the second voltage-controlled oscillator output.
Another approach to solve this problem is disclosed in U.S. patent application Ser. No.: 08/951,139, filed on Oct. 15, 1997, now patent No. 6,018,273 by the same inventor of the present application. The application is hereby incorporated by reference. The phase locked loop disclosed in the application is shown in FIG. 3.
Referring to FIG. 3, the phase locked loop comprises two voltage-controlled oscillators (i.e. a first voltage-controlled oscillator, and a second voltage-controlled oscillator) and a synchronizing circuit. In the phase locked loop as shown, the synchronizing circuit turns on the second voltage-controlled oscillator after a synchronizing pulse is received. When the first voltage-controlled oscillator completes a cycle, it is turned off. Next, after one full cycle of the second voltage-controlled oscillator, the first voltage-controlled oscillator is re-started such that it is synchronized with the second voltage-controlled oscillator and thus with the synchronizing pulse. In this manner, the output of the first voltage-controlled oscillator is both synchronized with the synchronizing pulse and controlled by a feedback circuitry connected to the output of the first voltage-controlled oscillator. Since the output of the feedback circuit is used to control the voltage-controlled oscillator which produces the output of the circuit, the differing parameter characteristics of the first and second voltage-controlled oscillators is less of a problem. The timing period controlled by the second voltage-controlled oscillator is relatively short so the error caused by the parameter differences does not accumulate. Even though this method provides the desirable results of producing a clock output both running at substantially identical frequency as with the system clock and synchronizing with the synchronizing pulse, this method requires two voltage-controlled oscillators which is not preferred in some application.
Therefore, it is desired to have a phase locked loop system using a single voltage-controlled oscillator capable of generating a clock output both running at substantially identical frequency with the system clock and also synchronizing with the synchronizing pulse.